Consider the logic circuit given below.

The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable?
(A) 5
(B) 11
(C) 16
(D) 17


Answer: (A)

Explanation: In this circuit, inverter and the AND gate will take total 16 nsecs (6 nsecs will be taken by inverter and another 10 nsecs by AND gate) to reach the XOR gate whereas the OR gate will reach to the XOR gate in only 11 nsecs, which will cause a glitch to happen for 5 nsecs.

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