Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

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Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?
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(A) a
(B) b
(C) c
(D) d


Answer: (C)

Explanation:
Q0 = 0 (given)
Therefore, Q0\’ = 1

During the first clock cycle nothing will change since input doesn\’t come before rising edge of the clock cycle
Q0\’ becomes ’0’ on rising edge of next clock cycle. Therefore, for only one clock cycle D1 will be ‘1’.

 
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Thus, option (C) is the answer.

 
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  • Last Updated : 19 Nov, 2018

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