In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
(A) Q = 0, Q\’ = 1
(B) Q = 1, Q\’ = 0
(C) Q = 1, Q\’ = 1
(D) Indeterminate states
Answer: (D)
Explanation: If both R reset and S set inputs are inactivated. It means made ‘0’, both Q and Q’ tend to be ‘1’. [NAND gate characteristic is that only when both inputs are 1,the output is 0.] The logic of the circuit (Q’ is complement of Q) not satisfied, and the final state at an instant after inputs R and S changed to ‘0’, is only a matter of chance. Logic state is said to be indeterminate state or racing state. Each state, Q =‘1’and Q =‘0’, and Q =‘0’, Q=‘1’ trying to race through so “RACE CONDITION” occurs and output become unstable. So ans is (D) part.
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